The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for the capacitor plates is conductively doped silicon, such as polysilicon. Such material is so utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying topography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material electrically conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper silicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such techniques are inherently unpredictable or inconsistent in the production of a rugged silicon film.
FIG. 1 illustrates a prior art plot of a silicon deposition process utilizing silane and hydrogen as source gases as a function of deposition pressure and deposition temperature. The upper or far left illustrated line "A" is the interface line between whether the deposition produces amorphous silicon or a mixed phase of crystalline and amorphous silicon. At combination deposition pressures and temperatures falling above or to the left of line "A", the deposited layer will be essentially amorphous. At combination deposition pressures and temperatures falling below or to the right of the line "A" and above and to the left of line "B", the deposition will be mixed phase. The interface line "B" is a boundary between rough versus smooth outer surface silicon of either mixed or crystalline phases. Those deposition pressure and temperature combinations falling between the illustrated lines "A" and "B" produce mixed phase silicon having an inherently rough outer surface. Those deposition pressure and temperature combinations falling to the right or below the illustrated line "B" produce polysilicon films having inherently smooth outer surfaces. Amorphous silicon films deposited to the left or above the line "A" are generally smooth.
The goal for the processor when desiring to deposit a rough polycrystalline film is to fall within or between the two illustrated "A" and "B" lines. Ultimate subsequent wafer processing, which includes heating, will transform such film into rough polysilicon. However, processing control and other parameters can adversely affect the controllability of producing a silicon film falling within the "A" and "B" line boundaries in situ having rough outer surfaces.
The prior art also recognizes that rough polysilicon films can be produced by post-deposition vacuum anneal. Using this method, surface roughness can be induced after a lower capacitor plate electrode is defined by photopatterning and etching. However, such anneal processes require careful surface control and high vacuum leading to difficulties in processing.
Accordingly, it would be desirable to improve upon these and other prior art processes in methods of forming polysilicon layers having roughened outer surfaces.